| Subject: | key word problem |
| Date: | Fri, 6 Nov 2009 16:54:03 +0800 |
| To: | <bug-verilog-perl [...] rt.cpan.org> |
| From: | 陳 Walter <weigianc [...] hotmail.com> |
the verilog::netlist do not deal the case smoothly:
module a (
bit,
byte,
bus,
in
);
output bit;
output [7:0] byte;
output [1:0] bus;
input in;
endmodule
it complaint about bit and byte and think they are some verilog keyword or so.
the error message is:
%Error: a.v:4: syntax error, unexpected NETTYPE keyword (tri0/wand/etc), expecting inout or input or output or ref
Exiting due to errors
the perl version is 5.10.0