| Subject: | Errors in assembled code |
Thanks for this module.
I have tested the assembled code by this module against the test file of
z80pack-1.13 (ftp://ftp.unix4fun.org/z80pack/) and found a couple of
problems:
1. z80masm needs to open output file in binary mode. Added test case
that failed in Windows before the correction.
2. "LD (IX+0x56),0x26" returns "0xDD 0x36 0x56" instead of "0xDD 0x36
0x56 0x26"
3. "LD (IY+0x56),0x26" returns "0xFD 0x36 0x56" instead of "0xFD 0x36
0x56 0x26"
4. "SBC A,(HL)" returns "0xDE 0x00" instead of "0x9E"
5. "SBC A,A" returns "0xDE 0x00" instead of "0x9F"
6. "SRL (IX+0x56)" fails with "Invalid instruction"
7. "SRL (IY+0x56)" fails with "Invalid instruction"
8. t\00-opcodes.t does not return error code on failure of a test case.
9. t\00-opcodes.t has wrong assembly sequence for "LD (IX+0x56),0x26",
"LD (IY+0x56),0x26"
10. t\00-opcodes.t defines "SBC (HL)" and "SBC A" instead of "SBC
A,(HL)" and "SBC A,A".
11. t\00-opcodes.t misses "SRL (IX+0x56)" and "SRL (IY+0x56)"
The attached patch fixes these problems and adds test cases to detect them.
Module : D/DC/DCANTRELL/CPU-Z80-Assembler-1.01.tar.gz
Perl : This is perl, v5.8.8 built for MSWin32-x86-multi-thread
Best regards,
Paulo Custodio
| Subject: | CPU-Z80-Assembler-patch-1.01-1.01a.txt |
diff -rc CPU-Z80-Assembler-1.01/MANIFEST CPU-Z80-Assembler-1.01a/MANIFEST
*** CPU-Z80-Assembler-1.01/MANIFEST Sat Jun 14 18:26:40 2008
--- CPU-Z80-Assembler-1.01a/MANIFEST Sat Jun 21 22:29:02 2008
***************
*** 10,15 ****
--- 10,16 ----
t/01-DEF-instrs.t
t/02-labels.t
t/03-macros.t
+ t/04-binmode.t
GPL2.txt
ARTISTIC.txt
META.yml Module meta-data (added by MakeMaker)
diff -rc CPU-Z80-Assembler-1.01/Makefile.PL CPU-Z80-Assembler-1.01a/Makefile.PL
*** CPU-Z80-Assembler-1.01/Makefile.PL Sat Jun 14 18:26:14 2008
--- CPU-Z80-Assembler-1.01a/Makefile.PL Sat Jun 21 22:10:18 2008
***************
*** 5,11 ****
NAME => 'CPU::Z80::Assembler',
VERSION_FROM => 'lib/CPU/Z80/Assembler.pm',
PREREQ_PM => {
! 'Test::More' => 0
},
EXE_FILES => [qw(
bin/z80masm
--- 5,13 ----
NAME => 'CPU::Z80::Assembler',
VERSION_FROM => 'lib/CPU/Z80/Assembler.pm',
PREREQ_PM => {
! 'Test::More' => 0,
! 'File::Slurp' => 0,
! 'File::Spec' => 0,
},
EXE_FILES => [qw(
bin/z80masm
diff -rc CPU-Z80-Assembler-1.01/bin/z80masm CPU-Z80-Assembler-1.01a/bin/z80masm
*** CPU-Z80-Assembler-1.01/bin/z80masm Fri Jun 13 21:29:26 2008
--- CPU-Z80-Assembler-1.01a/bin/z80masm Sat Jun 21 22:12:33 2008
***************
*** 11,16 ****
--- 11,17 ----
open(IN, $infile) || die("Can't open $infile\n");
open(OUT, ">$outfile") || die("Can't open $outfile\n");
+ binmode(OUT);
print OUT z80asm(<IN>);
close(OUT);
close(IN);
diff -rc CPU-Z80-Assembler-1.01/lib/CPU/Z80/Assembler.pm CPU-Z80-Assembler-1.01a/lib/CPU/Z80/Assembler.pm
*** CPU-Z80-Assembler-1.01/lib/CPU/Z80/Assembler.pm Sat Jun 14 18:26:06 2008
--- CPU-Z80-Assembler-1.01a/lib/CPU/Z80/Assembler.pm Sat Jun 21 22:34:39 2008
***************
*** 8,14 ****
use vars qw($VERSION @EXPORT $verbose);
! $VERSION = '1.01';
use base qw(Exporter);
--- 8,14 ----
use vars qw($VERSION @EXPORT $verbose);
! $VERSION = '1.01a';
use base qw(Exporter);
***************
*** 652,657 ****
--- 652,660 ----
_write($address + 1, 0x9E);
_write($address + 2, _to_number($2));
$address += 3;
+ } elsif($r1 eq 'A' && exists($TABLE_R{$r2})) {
+ _write($address, 0x98 + $TABLE_R{$r2});
+ $address += 1;
} elsif($r1 eq 'A') {
_write($address, 0xDE);
_write($address + 1, _to_number($r2));
***************
*** 846,852 ****
} else {
_write($address + 1, 0x36);
_write($address + 2, _to_number($offset));
! $address += 3;
}
} elsif($r1 =~ /\((.*)\)/) { # target (addr)
my $target = $1;
--- 849,856 ----
} else {
_write($address + 1, 0x36);
_write($address + 2, _to_number($offset));
! _write($address + 3, _to_number($r2));
! $address += 4;
}
} elsif($r1 =~ /\((.*)\)/) { # target (addr)
my $target = $1;
***************
*** 980,985 ****
--- 984,995 ----
_write($address , 0xCB);
_write($address + 1, 0x38 + $TABLE_R{$params});
$address += 2;
+ } elsif($params =~ /\((I[XY])(.*?)\)/) {
+ _write($address, $1 eq 'IX' ? 0xDD : 0xFD);
+ _write($address + 1, 0xCB);
+ _write($address + 2, _to_number($2));
+ _write($address + 3, 0x3E);
+ $address += 4;
}
}
sub _STOP {
diff -rc CPU-Z80-Assembler-1.01/t/00-opcodes.t CPU-Z80-Assembler-1.01a/t/00-opcodes.t
*** CPU-Z80-Assembler-1.01/t/00-opcodes.t Tue Jun 17 18:31:08 2008
--- CPU-Z80-Assembler-1.01a/t/00-opcodes.t Sat Jun 21 22:57:08 2008
***************
*** 4,32 ****
use warnings;
use CPU::Z80::Assembler;
! print "1..712\n";
! my $test = 1;
! my @codes = map { $_ =~ s/^\s+|\s+$//g; $_ } grep { /\S/ && $_ !~ /^\s+#/ } <DATA>;
foreach my $code (@codes) {
! (my $expectedbytes = $code) =~ s/^.*;\s+//;
my $expectedbinary = join(
'',
map {
chr(eval "0x$_")
! } split(/\s+/, $expectedbytes)
);
! my $binary = eval { z80asm("ORG 0x6789\n$code") } || 'xxxxxx';
! print "not " unless($binary eq $expectedbinary);
! print "ok ".($test++)." - $code";
! print ' (got '.join(' ', map { sprintf("0x%02X", ord($_)) } split(//, $binary)).')' unless($binary eq $expectedbinary);
! print "\n";
! print "# $@" if($@);
}
! __DATA__
STOP ; DD DD 00
ADC A,(HL) ; 8E
--- 4,33 ----
use warnings;
use CPU::Z80::Assembler;
! use Test::More tests => 1428;
! my @codes = map { $_ =~ s/^\s+|\s+$//g; $_ } grep { s/\s*\#.*//; /\S/ } <DATA>;
foreach my $code (@codes) {
! (my $expectedbytes = $code) =~ s/^.*;\s*//;
my $expectedbinary = join(
'',
map {
chr(eval "0x$_")
! } split(" ", $expectedbytes)
);
! my $binary = eval { z80asm("ORG 0x6789\n$code") };
! is $@, "",
! "eval $code";
! is hexdump($binary), hexdump($expectedbinary),
! "result $code";
}
! sub hexdump {
! return join(' ', map { sprintf("0x%02X", ord($_)) } split(//, shift));
! }
+ __DATA__
STOP ; DD DD 00
ADC A,(HL) ; 8E
***************
*** 208,213 ****
--- 209,215 ----
EX (SP),IX ; DD E3
EX (SP),IY ; FD E3
EX AF,AF' ; 08
+ # close quote to keep editor happy'
EX DE,HL ; EB
HALT ; 76
IM 0 ; ED 46
***************
*** 289,295 ****
LD (HL),E ; 73
LD (HL),H ; 74
LD (HL),L ; 75
! LD (IX+0x56),0x56 ; DD 36 56
LD (IX+0x56),A ; DD 77 56
LD (IX+0x56),B ; DD 70 56
LD (IX+0x56),C ; DD 71 56
--- 291,297 ----
LD (HL),E ; 73
LD (HL),H ; 74
LD (HL),L ; 75
! LD (IX+0x56),0x26 ; DD 36 56 26
LD (IX+0x56),A ; DD 77 56
LD (IX+0x56),B ; DD 70 56
LD (IX+0x56),C ; DD 71 56
***************
*** 297,303 ****
LD (IX+0x56),E ; DD 73 56
LD (IX+0x56),H ; DD 74 56
LD (IX+0x56),L ; DD 75 56
! LD (IY+0x56),0x56 ; FD 36 56
LD (IY+0x56),A ; FD 77 56
LD (IY+0x56),B ; FD 70 56
LD (IY+0x56),C ; FD 71 56
--- 299,305 ----
LD (IX+0x56),E ; DD 73 56
LD (IX+0x56),H ; DD 74 56
LD (IX+0x56),L ; DD 75 56
! LD (IY+0x56),0x26 ; FD 36 56 26
LD (IY+0x56),A ; FD 77 56
LD (IY+0x56),B ; FD 70 56
LD (IY+0x56),C ; FD 71 56
***************
*** 595,602 ****
RST 5 ; EF
RST 6 ; F7
RST 7 ; FF
! SBC (HL) ; 9E
! SBC A ; 9F
SBC A,(IX+0x56) ; DD 9E 56
SBC A,(IY+0x56) ; FD 9E 56
SBC A,0x56 ; DE 56
--- 597,604 ----
RST 5 ; EF
RST 6 ; F7
RST 7 ; FF
! SBC A,(HL) ; 9E
! SBC A,A ; 9F
SBC A,(IX+0x56) ; DD 9E 56
SBC A,(IY+0x56) ; FD 9E 56
SBC A,0x56 ; DE 56
***************
*** 712,717 ****
--- 714,721 ----
SRA H ; CB 2C
SRA L ; CB 2D
SRL (HL) ; CB 3E
+ SRL (IX+0x56) ; DD CB 56 3E
+ SRL (IY+0x56) ; FD CB 56 3E
SRL A ; CB 3F
SRL B ; CB 38
SRL C ; CB 39
Only in CPU-Z80-Assembler-1.01a/t: 04-binmode.t