| Subject: | nested macros are not expanded correctly if a macro has arguments ... |
| Date: | Sun, 13 Apr 2008 08:55:09 -0700 (PDT) |
| To: | bug-Verilog-Perl [...] rt.cpan.org |
| From: | Vladimir Matveyenko <admin [...] matveyenko.com> |
distribution: Verilog-Perl-3.024.tar.gz
Perl version: v5.8.5 built for x86_64-linux
OS: Linux * 2.6.5-7.283-smp #1 SMP Wed Nov 29 16:55:53 UTC 2006 x86_64 x86_64 x86_64 GNU/Linux
I'm reporting an issue with macro expansion only on linux platform (see above), while works fine on Gygwin OS
(CYGWIN_NT-5.1 ecwm0clloan2 1.5.25(0.156/4/2) 2008-03-05 19:27 i686 Cygwin)
It seems that on linux, if a macro contains an argument and it is nested, it gets all confused.
Thanks.
Here is the verilog code to duplicate the issue: test1.vs
// ----------------------------------------------------------//
`define ADD1A(a) \
`ifdef SIM \
always @(*) a = a + 1; \
`else \
p22add add_1 (a) \
`endif
`define ADD1B \
`ifdef SIM \
always @(*) a = a + 1; \
`else \
p22add add_1 (a) \
`endif
module test1 (input logic a);
/* this macro will not expand correctly */
`ADD1A(a)
/* this macro will expand correctly */
`ADD1B
endmodule
// -----------------------------------------------------------//
// -----------------------------------------------------------//
Here is the result of expansion on Linux (incorrect)
// -----------------------------------------------------------//
Show quoted text
168>vppp +define+SIM --simple test1.vs
module test1 (input logic a);
ifdef` SIM always @(*) a = a + 1; else` p22add add_1 (a) endif`
always @(*) a = a + 1;
endmodule
// -----------------------------------------------------------//
Here is the result of expansion on Cygwin OS:
// -----------------------------------------------------------//
10 $ vppp +define+SIM --simple test1.vs
module test1 (input logic a);
always @(*) a = a + 1;
always @(*) a = a + 1;
endmodule