Index: Parser/VParseBison.y
===================================================================
--- Parser/VParseBison.y (revision 53189)
+++ Parser/VParseBison.y (working copy)
@@ -324,15 +324,13 @@
%type<str> instModName
%type<str> instRangeE
%type<str> portRangeE
+%type<str> portV2kInit
%type<str> portV2kSig
%type<str> rangeList
%type<str> rangeListE
%type<str> sigAndAttr
%type<str> sigId
%type<str> strAsInt
-%type<str> varInout
-%type<str> varInput
-%type<str> varOutput
%type<str> varRefBase
%type<str> varRefDotBit
%type<str> varTypeKwds
@@ -424,9 +422,13 @@
// Called only after a comma in a v2k list, to allow parsing "input a,b"
portV2kSecond: portV2kDecl { }
- | portV2kSig { }
+ | portV2kInit { }
;
+portV2kInit: portV2kSig { }
+ | portV2kSig '=' expr { }
+ ;
+
portV2kSig: sigAndAttr { $<fl>$=$<fl>1; PARSEP->portCb($<fl>1, $1); }
;
@@ -453,7 +455,7 @@
;
// IEEE: interface_item + non_port_interface_item
-interfaceItem:
+interfaceItem:
varDecl { }
| generateRegion { }
| interfaceOrGenerateItem { }
@@ -508,14 +510,6 @@
//| method_prototype
;
-//IEEE: port_direction
-portDirection: varInput { }
- | varOutput { }
- | varInout { }
- | varRef { }
- ;
-
-
//************************************************
// Variable Declarations
@@ -527,17 +521,13 @@
| regsigList ',' regsig { }
;
-portV2kDecl: varRESET varInput v2kVarDeclE signingE regArRangeE portV2kSig { }
- | varRESET varInout v2kVarDeclE signingE regArRangeE portV2kSig { }
- | varRESET varOutput v2kVarDeclE signingE regArRangeE portV2kSig { }
+portV2kDecl: varRESET portDirection v2kVarDeclE signingE regArRangeE portV2kInit { }
// | varRESET yaID portV2kSig { }
// | varRESET yaID '.' yaID portV2kSig { }
;
// IEEE: port_declaration - plus ';'
-portDecl: varRESET varInput v2kVarDeclE signingE regArRangeE sigList ';' { }
- | varRESET varInout v2kVarDeclE signingE regArRangeE sigList ';' { }
- | varRESET varOutput v2kVarDeclE signingE regArRangeE sigList ';' { }
+portDecl: varRESET portDirection v2kVarDeclE signingE regArRangeE regsigList ';' { }
;
varDecl: varRESET varReg signingE regArRangeE regsigList ';' { }
@@ -570,14 +560,13 @@
varReg: yREG { VARDECL($1); }
| varTypeKwds { VARDECL($1); }
;
-varInput: yINPUT { VARIO($1); }
+
+//IEEE: port_direction
+portDirection: yINPUT { VARIO($1); }
+ | yOUTPUT { VARIO($1); }
+ | yINOUT { VARIO($1); }
+ | yREF { VARIO($1); }
;
-varOutput: yOUTPUT { VARIO($1); }
- ;
-varInout: yINOUT { VARIO($1); }
- ;
-varRef: yREF { VARIO($1); }
- ;
varTypeKwds: yINTEGER { $<fl>$=$<fl>1; $$=$1; }
| yREAL { $<fl>$=$<fl>1; $$=$1; }
@@ -782,10 +771,14 @@
sigId: yaID { $<fl>$=$<fl>1; VARDONE($<fl>1, $1, ""); }
;
-sigList: sigAndAttr { }
- | sigList ',' sigAndAttr { }
+sigList: sigInit { }
+ | sigList ',' sigInit { }
;
+sigInit: sigAndAttr { }
+ | sigAndAttr '=' expr { }
+ ;
+
regsig: regSigId sigAttrListE {}
;
Index: t/35_sigparser.out
===================================================================
--- t/35_sigparser.out (revision 53189)
+++ t/35_sigparser.out (working copy)
@@ -239,6 +239,16 @@
verilog/parser_bugs.v:243: SIGNAL_DECL 'wire' 'c' '' '' '' ''
verilog/parser_bugs.v:243: SIGNAL_DECL 'wire' 'd' '' '' '' ''
verilog/parser_bugs.v:248: ENDMODULE 'endmodule'
+verilog/parser_bugs.v:250: MODULE 'module' 'bug34649' undef '0'
+verilog/parser_bugs.v:250: PORT 'name'
+verilog/parser_bugs.v:251: SIGNAL_DECL 'output' 'name' '' '' '' ''
+verilog/parser_bugs.v:251: SIGNAL_DECL 'reg' 'name' '' '' '' '0'
+verilog/parser_bugs.v:252: ENDMODULE 'endmodule'
+verilog/parser_bugs.v:253: MODULE 'module' 'bug34649b' undef '0'
+verilog/parser_bugs.v:254: SIGNAL_DECL 'output' 'name' '' '' '' ''
+verilog/parser_bugs.v:254: SIGNAL_DECL 'reg' 'name' '' '' '' ''
+verilog/parser_bugs.v:254: PORT 'name'
+verilog/parser_bugs.v:256: ENDMODULE 'endmodule'
verilog/pinorder.v:006: MODULE 'module' 'pinorder4' undef '0'
verilog/pinorder.v:007: SIGNAL_DECL 'wire' 'b_i' '' '' '' ''
verilog/pinorder.v:008: SIGNAL_DECL 'wire' 'd_o' '' '' '' ''
Index: verilog/parser_bugs.v
===================================================================
--- verilog/parser_bugs.v (revision 53189)
+++ verilog/parser_bugs.v (working copy)
@@ -246,3 +246,11 @@
assign #(0:1:2,0:1:2) c = 1;
assign #(0:1:2,0) d = 1;
endmodule
+
+module bug34649 (name);
+ output reg name = 0;
+endmodule
+module bug34649b (
+ output reg name = 0
+ );
+endmodule
Index: Changes
===================================================================
--- Changes (revision 53189)
+++ Changes (working copy)
@@ -5,6 +5,8 @@
* Verilog::Language 3.02***
+**** Fix "output reg name=expr;" bug34649 syntax error. [Martin Scharrer]
+
**** Fix functions with "input integer". [Johan Wouters]
* Verilog::Language 3.024 2008/04/02
