| Subject: | Bug in Verilog-Perl - MIN:TYP:MAX delays in assign |
| Date: | Mon, 31 Mar 2008 16:31:36 +0100 |
| To: | bug-Verilog-Perl [...] rt.cpan.org |
| From: | Martin Scharrer <martin [...] scharrer-online.de> |
Hello,
I'm using the tool 'vhier' included in Verilog-Perl which uses
Verilog::Language to print the hierarchy of my Verilog files. My code is
mostly Verilog1995 with some minor exceptions in some test-bench files
where I use the 'generate' block.
The used versions are
Perl 5.8.8
vhier: # $Id: vhier 49328 2008-01-07 16:28:25Z wsnyder $
Verilog-Perl-3.023 from CPAN
The parser can't handle assignments which uses the MIN:TYP:MAX delay
syntax for falling and rising edges.
Please see the example below:
module test;
wire a,b,c,d;
assign #(0,0) a = 1; // Works
assign #(0:1:2) b = 1; // Works
assign #(0:1:2,0:1:2) c = 1; // Does not work
assign #(0:1:2,0) d = 1; // Does not work
endmodule
%Error: test.v:5: syntax error, unexpected ',', expecting ')'
Exiting due to errors
This is valid Verilog code in my opinion.
Thank you,
Martin Scharrer