| Subject: | Verilog::SigParaser does not take prepocessed output |
I am trying to use the Verilog-Perl package for parsing some verilog files .
But when I try and pass preprocessed output to SigParser (as described
in package synopsys) object I get error shown below.
Kindly let me know how to resolve this.
I have attached the perl script for ref.
Can't locate auto/Verilog/SigParser/parse_prepo.al in @INC (@INC
contains: /usr/lib/perl5/5.8/cygwin /usr/lib/perl5/5.8
/usr/lib/perl5/site_perl/5.8/cygwin /usr/lib/perl5/site_perl/5.8
/usr/lib/perl5/site_perl/5.8/cygwin /usr/lib/perl5/site_perl/5.8
/usr/lib/perl5/vendor_perl/5.8/cygwin /usr/lib/perl5/vendor_perl/5.8
/usr/lib/perl5/vendor_perl/5.8/cygwin /usr/lib/perl5/vendor_perl/5.8 .)
at ./vp11.pl line 16
| Subject: | vp11.pl |
#!/usr/bin/perl -w
use Verilog::Preproc;
use Verilog::SigParser;
my $pp = Verilog::Preproc->new(keep_comments=>0,keep_whitespaces=>0,line_directives=>0,);
$pp->open(filename=>"i2c_blk_ver.v");
while (defined (my $line = $pp->getline())){
print $line;
}
my $parser = new Verilog::SigParser;
$parser->parse_prepoc_file($pp);