| Subject: | Verilog Perl does not parse widths correctly |
| Date: | Thu, 26 Jul 2007 15:24:39 -0700 |
| To: | <bug-Verilog-Perl [...] rt.cpan.org> |
| From: | "Vinod Ananth" <vananth [...] marvell.com> |
Hi,
I found the following problem when trying to parse a Verilog file using
Verilog::Netlist
One of the ports in the module is defined like this
input [32-1:0] DATA_IN;
When the parser hits that line, it prints the following message
Argument "32-1" isn't numeric in subtraction (-) at <lib path>/Net.pm
line 35
(This is valid Verilog syntax though)
When I then try to get the width of this signal, it shows 33 instead of
32.
Thanks
Vinod