| Subject: | Problem with list of memories |
In the attached file, registers "a_fifo_cam_indices" and
"lt_fifo_cam_indices" do not have their memory bounds correctly
initialized when Verilog::SigParser calls the signal_decl callback.
Furthermore, the vector comes in as "[2:0] [3:0] [3:0]".
| Subject: | lh_memcat.v |