Subject: | Combined wire declaration/assignments |
A wire declaration that combines an assignment results in incorrect
information being passed to signal_decl.
In the attached file, signal_decl gets called correctly with "b[0:3]"
and then incorrectly with "a[2]" and "b[2]" (a re-declaration).
Using perl5.8.0 and perl 5.8.8 on Linux.
Subject: | wireassign.v |