Bug #25833 for Verilog-Perl: Fails to parse first statement after null port list

Mon Mar 26 18:20:45 2007 nodine [...] cpan.org - Ticket created

Subject:

Fails to parse first statement after null port list

The Verilog::SigParser never calls the signal_decl routine for the declaration of reg "a". The problem is that $self->{is_signal_ok} is false at the time the semicolon after the register declaration is processed. This can be traced back to the line that says # Fallthru, more ; prep for next command is below which does not, in fact, fall through to the rest of the ';' processing.

Subject:

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Thu Mar 29 14:30:46 2007 wsnyder [...] wsnyder.org - Status changed from 'new' to 'open'

Thu Mar 29 16:19:56 2007 wsnyder [...] wsnyder.org - Correspondence added

On Mon Mar 26 18:20:45 2007, NODINE wrote: Show quoted text

> The Verilog::SigParser never calls the signal_decl routine for the > declaration of reg "a". The problem is that $self->{is_signal_ok} is > false at the time the semicolon after the register declaration is > processed. This can be traced back to the line that says

I agree that's probably a problem, but the only place is_signal_ok is set to 0 looks to be dead code. When I run your verilog code using a hacked version of t/35_sigparser.t I see all of the signals. Can you send me an example script that is broken? BTW I'm sorry the parser isn't bison'ized yet.

Thu Mar 29 16:20:02 2007 wsnyder [...] wsnyder.org - Given to WSNYDER

Thu Mar 29 16:49:28 2007 nodine [...] intrinsity.com - Correspondence added

Subject:	Re: [rt.cpan.org #25833] Fails to parse first statement after null port list
Date:	Thu, 29 Mar 2007 15:43:02 -0500
To:	bug-Verilog-Perl [...] rt.cpan.org
From:	Mark Nodine <nodine [...] intrinsity.com>

via RT wrote: Show quoted text

> <URL: http://rt.cpan.org/Ticket/Display.html?id=25833 > > > On Mon Mar 26 18:20:45 2007, NODINE wrote:

>> The Verilog::SigParser never calls the signal_decl routine for the >> declaration of reg "a". The problem is that $self->{is_signal_ok} is >> false at the time the semicolon after the register declaration is >> processed. This can be traced back to the line that says

> > I agree that's probably a problem, but the only place is_signal_ok is > set to 0 looks to be dead code. > > When I run your verilog code using a hacked version of t/35_sigparser.t > I see all of the signals. Can you send me an example script that is broken?

When I worked on a simple example, it was fine. When I ran my full program using perl 5.8.8 instead of 5.8.0, it was fine. The full script failed on 5.8.0. So I guess you shouldn't worry about it. Sorry to trouble you. --Mark

Tue Apr 03 09:13:46 2007 wsnyder [...] wsnyder.org - Correspondence added 5 min

I've released 2.373 which fixes this bug.

Tue Apr 03 09:13:55 2007 wsnyder [...] wsnyder.org - Status changed from 'open' to 'resolved'

Bug #25833 for Verilog-Perl: Fails to parse first statement after null port list

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