| Subject: | wire declaration is wrong when add new net |
| Date: | Thu, 25 Jan 2007 13:40:53 +0900 |
| To: | bug-Verilog-Perl [...] rt.cpan.org |
| From: | Takeo Komiyama <takeo.komiyama [...] freescale.com> |
Hi,
I found the strange behavior in Verilog-Perl 2.370 release.
When I add new wire using with new_net() function.
verilog_text() generate wrong verilog sytax code (missing wire declaration).
Show quoted text
----- Test code ------------------------------
#! /usr/bin/env perl
use strict;
use Verilog::Netlist;
use Verilog::Netlist::Net;
my $nl = new Verilog::Netlist (keep_comments=>1);
$nl->read_file (filename=>"test.v");
$nl-> link();
my $module = $nl -> find_module ("test");
my $newNet = $module -> new_net (name=>"new_wire");
print $module -> verilog_text();
----- Test code ------------------------------
----- Test data ------------------------------
module top;
wire a;
wire b;
test inst1
(.a(a),
.b(b)
);
endmodule
module test (
input a,
output b
);
endmodule
----- Test data ------------------------------
Above sample generate,
user@hoge[130]% ./test.pl
module test (
a, b);
input a;
output b;
new_wire; <---- Here. No wire declaration.
endmodule
So, I modified Verilog::Netlist::Net as,
--------- Patch -------------------------------------------
*** Net.pm~ 2007-01-22 21:28:00.000000000 +0900
--- Net.pm 2007-01-22 21:28:18.000000000 +0900
***************
*** 110,115 ****
--- 110,119 ----
$type = "output" if $self->port->direction eq "out";
$type = "inout" if $self->port->direction eq "inout";
}
+ else
+ {
+ $type = "wire";
+ }
$type .= " signed" if $self->signed;
return $type;
}
--------- Patch -------------------------------------------
Then I confirm this problem is fixed.
module test (
a, b);
input a;
output b;
wire new_wire;
endmodule
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event I
create account. So I directory sent this message.