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This queue is for tickets about the Verilog-VCD-Writer CPAN distribution.

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The Basics
Id: 123724
Status: open
Priority: 0/
Queue: Verilog-VCD-Writer
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Owner: Nobody in particular
Requestors: michaelsundmlis [...] gmail.com
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Bug Information
Severity: (no value)
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Fixed in: (no value)

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  Thu Nov 23 16:23:16 2017 michaelsundmlis [...] gmail.com - Ticket created
Subject: Bugs about verilog vcd writer
Date: Thu, 23 Nov 2017 16:23:02 -0500
To: "bug-Verilog-VCD-Writer [...] rt.cpan.org" <bug-Verilog-VCD-Writer [...] rt.cpan.org>
From: <michaelsundmlis [...] gmail.com>
use Verilog::VCD::Writer; By copyting the Synopsis code directly, it could not pass. 1) With this, not all commands under it will be loaded. In the synopsis, addSignal is the module under Verilog::VCD::Writer::Module. As a result, the code on Synopsis will raise an error directly, as perl cannot find addSignal directly under writer.pm Can't locate object method "addSignal" via package "Verilog::VCD::Writer" at tester.pl line 6. 2) In module.pm, addSignal module, line 41, $self->signals_push($s) cannot activate the command “push”. It will raised the error such that Can't locate object method "signals_push" via package "Verilog::VCD::Writer" at /home/cqsun/lib/perl5/lib/site_perl/5.18.2/Verilog/VCD/Writer/Module.pm line 41. Please contact me as soon as possible about the errors or my mistakes. Sincerely, Chuanqi Sun
  Tue Dec 12 15:57:08 2017 gsullivan [...] cpan.org - Correspondence added
This patch should fix the errors in the SYNOPSIS code.
Subject: diff-u.txt
--- ../Verilog-VCD-Writer-0.002.orig/lib/Verilog/VCD/Writer.pm 2017-05-23 20:22:04.000000000 -0400 +++ lib/Verilog/VCD/Writer.pm 2017-12-12 15:49:50.467386000 -0500 @@ -130,26 +130,26 @@ =head1 SYNOPSIS - use Verilog::VCD::Writer; + use Verilog::VCD::Writer; - my $writer=Verilog::VCD::Writer->new(timescale=>'1 ns',vcdfile=>"test.vcd"); - $writer->addComment("Author:Vijayvithal"); + my $writer = Verilog::VCD::Writer->new(timescale=>'1 ns',vcdfile=>"test.vcd"); + $writer->addComment("Author:Vijayvithal"); - my $top=$writer->addModule("top"); # Create toplevel module - my $TX=$writer->addSignal("TX",7,0); #Add Signals to top - my $RX=$writer->addSignal("RX",7,0); - - my $dut=$top->addModule("DUT"); Create SubModule - $dut->dupSignal($TX,"TX",7,0); #Duplicate signals from Top in submodule - $dut->dupSignal($RX,"RX",7,0); - - $writer->writeHeaders(); # Output the VCD Header. - $writer->setTime(0); # Time 0 - $writer->addValue($TX,0); # Record Transition - $writer->addValue($RX,0); - $writer->setTime(5); # Time 1ns - $writer->addValue($TX,1); - $writer->addValue($RX,0); + my $top = $writer->addModule("top"); # Create toplevel module + my $TX = $top->addSignal("TX",7,0); #Add Signals to top + my $RX = $top->addSignal("RX",7,0); + + my $dut = $writer->addModule("DUT"); #Create SubModule + $dut->dupSignal($TX,"TX",7,0); #Duplicate signals from Top in submodule + $dut->dupSignal($RX,"RX",7,0); + + $writer->writeHeaders(); # Output the VCD Header. + $writer->setTime(0); # Time 0 + $writer->addValue($TX,0); # Record Transition + $writer->addValue($RX,0); + $writer->setTime(5); # Time 1ns + $writer->addValue($TX,1); + $writer->addValue($RX,0); =head1 METHODS
  Tue Dec 12 15:57:09 2017 The RT System itself - Status changed from 'new' to 'open'